![]() ![]() Very large scale integration (VLSI) applications have improved control implementation performance. Experimental results with some ISPD benchmarks show successful completion of global routing of all the nets with nominal wirelength values and complete intersection removal between the nets. (iii) Then removal of one of the intersecting edges creates two isolated same coloured polygons, those are connected via L shaped rectilinear path avoiding intersection. Overlapping polygons are marked with two different colours. (ii) Next, intersection between two different nets are detected based on a polygon overlap method. ![]() construct initial minimal rectilinear Steiner tree. (i) First a shortest path based heuristic approach is adopted to. Our proposed method comprises of the following steps. In this paper, we propose a heuristic method to perform global routing of multiple nets avoiding intersection between two nets. With the new era of VLSI design deviating greatly from Moore's law, a chip layout consists of a large number of nets routed on the metal layers. ![]()
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